system verilog - SystemVerilog memory coding style -

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i've coded 2 versions of single-port synchronous ram variable read/write width. however, first design results in 1307 alms utilization, while second results in 757 alms utilization, both compiled quartus prime 16.0.0 build 211 lite edition. idea why?

first vesion:

typedef enum logic [2:0] {char, uchar, short, ushort, int} datatype;  module memory(input datatype datatype, input [31:0] storedata, input [6:0] address, input clock, store, write, output logic excep, output [31:0] loaddata);     logic [1:0][1:0][7:0] memory [0:31];      always_ff @(posedge clock)         case (datatype)             char:                 if (store) memory[address[6:2]][address[1]][address[0]] <= storedata[7:0];                  else loaddata <= {{24{memory[address[6:2]][address[1]][address[0]][7]}}, memory[address[6:2]][address[1]][address[0]]};              uchar:                 if (store) memory[address[6:2]][address[1]][address[0]] <= storedata[7:0];                  else loaddata <= {24'h0, memory[address[6:2]][address[1]][address[0]]};              short:                 if (address[0] != 1'h0) excep <= 1'h1;                  else if (store) memory[address[6:2]][address[1]] <= storedata[15:0];                  else loaddata <= {{16{memory[address[6:2]][address[1]][1][7]}}, memory[address[6:2]][address[1]]};              ushort:                 if (address[0] != 1'h0) excep <= 1'h1;                  else if (store) memory[address[6:2]][address[1]] <= storedata[15:0];                  else loaddata <= {16'h0, memory[address[6:2]][address[1]]};              int:                 if (address[1:0] != 2'h0) excep <= 1'h1;                  else if (store) memory[address[6:2]] <= storedata;                  else loaddata <= memory[address[6:2]];         endcase endmodule

second version:

typedef enum logic [2:0] {char, uchar, short, ushort, int} datatype;  module memory(input datatype datatype, input [31:0] storedata, input [6:0] address, input clock, store, write, output logic excep, output [31:0] loaddata);     logic [1:0][1:0][7:0] memory [0:31];      always_ff @(posedge clock)         case (datatype)             char:                 if (store)                     case (address[1:0])                         1'h0: memory[address[6:2]][0][0] <= storedata[7:0];                         2'h1: memory[address[6:2]][0][1] <= storedata[7:0];                         2'h2: memory[address[6:2]][1][0] <= storedata[7:0];                         2'h3: memory[address[6:2]][1][1] <= storedata[7:0];                     endcase                  else                     case (address[1:0])                         1'h0: loaddata <= {{24{memory[address[6:2]][0][0][7]}}, memory[address[6:2]][0][0]};                         1'h1: loaddata <= {{24{memory[address[6:2]][0][1][7]}}, memory[address[6:2]][0][1]};                         1'h2: loaddata <= {{24{memory[address[6:2]][1][0][7]}}, memory[address[6:2]][1][0]};                         1'h3: loaddata <= {{24{memory[address[6:2]][1][1][7]}}, memory[address[6:2]][1][1]};                     endcase              uchar:                 if (store)                     case (address[1:0])                         1'h0: memory[address[6:2]][0][0] <= storedata[7:0];                         2'h1: memory[address[6:2]][0][1] <= storedata[7:0];                         2'h2: memory[address[6:2]][1][0] <= storedata[7:0];                         2'h3: memory[address[6:2]][1][1] <= storedata[7:0];                     endcase                  else                     case (address[1:0])                         1'h0: loaddata <= {24'h0, memory[address[6:2]][0][0]};                         1'h1: loaddata <= {24'h0, memory[address[6:2]][0][1]};                         1'h2: loaddata <= {24'h0, memory[address[6:2]][1][0]};                         1'h3: loaddata <= {24'h0, memory[address[6:2]][1][1]};                     endcase              short:                 if (address[0] != 1'h0) excep <= 1'h1;                  else if (store)                     case (address[1])                         1'h0: memory[address[6:2]][0] <= storedata[15:0];                         2'h1: memory[address[6:2]][1] <= storedata[15:0];                     endcase                  else                     case (address[1])                         1'h0: loaddata <= {{16{memory[address[6:2]][0][1][7]}}, memory[address[6:2]][0]};                         1'h1: loaddata <= {{16{memory[address[6:2]][1][1][7]}}, memory[address[6:2]][1]};                     endcase              ushort:                 if (address[0] != 1'h0) excep <= 1'h1;                  else if (store)                     case (address[1])                         1'h0: memory[address[6:2]][0] <= storedata[15:0];                         2'h1: memory[address[6:2]][1] <= storedata[15:0];                     endcase                  else                     case (address[1])                         1'h0: loaddata <= {16'h0, memory[address[6:2]][0]};                         1'h1: loaddata <= {16'h0, memory[address[6:2]][1]};                     endcase              int:                 if (address[1:0] != 2'h0) excep <= 1'h1;                  else if (store) memory[address[6:2]] <= storedata;                  else loaddata <= memory[address[6:2]];         endcase endmodule


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