memory - VHDL - How to elegantly initialize an array of std_logic_vector? -

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i'm trying interface classic hd44780 lcd. have implemented local ram write data wish show on display.

i have defined ram in way:

type ram_type array (0 (16*2)-1) of std_logic_vector(7 downto 0); signal lcd_mem : ram_type;

i've tried initializing ram in way:

lcd_mem(0 6) <= x"45_72_72_6f_72_73_3a"; ...

but receive error on synthesis:

error (10515): vhdl type mismatch error @ display_ber.vhd(74): ram_type type not match string literal

is there way ellegantly initialize ram block in similar way ?

perhaps should use string type instead ?

yes there is. note definition of ram_type array of std_logic_vector. , x"45_72_72_6f_72_73_3a" hex string literal. these not same type, hence error.

so, have put value array of vectors. such as:

lcd_mem(0 6) <= (0 => x"45", 1 => x"72", 2 => x"72", 3 => x"6f", 4 => x"72", 5 => x"73", 6 => x"3a");

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